A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS

Abstract

In this paper, a current mode (CM) full-duplex simultaneous bidirectional (FD-SBD) transceiver has been presented for chip-to-chip interconnect. To enable simultaneous bidirectional communication, the transceiver incorporates a hybrid network in the receive path, which not only eliminates the transmitted signal but also its reflections due to channel imperfections. A front-end programmable active delay line (PADL) and an approximate impedance matching network (IMN) at replica end forms the hybrid network to move and reduce the echo from received signal (RX) sampling point. The architecture has been implemented using 65 nm CMOS technology for a short channel with 4.375 dB insertion loss at 7.5 GHz. Post-layout simulation of the bidirectional transceiver with the link, gives an energy efficiency of 1.8 pJ/b, at aggregate data rate of 26 Gb/s. � 2023 IEEE.