A 27-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS

Abstract

The conventional current-mode pseudo-random bit sequence (PRBS) generators suffer from high-power consumption, low output voltage swing and they are not directly compatible with the CMOS static logic circuit. To address this issue, this work proposes power-efficient, 27-1, 20-Gb/s, half-rate pseudo-random bit sequence(HR-PRBS) generators by employing current-integrating latch circuit topology using incomplete settling at 20-Gb/s data rate implemented in 1.2 V, 65 nm CMOS. The proposed current-integrating logic latch based PRBS implementations achieves low power consumption, high speed and high voltage swing thanks to incomplete settling behaviour of the CIL circuit topology. The proposed PRBS generator implementations employing current-integrating latch topology consumes power of 0.76-mW/Gb/s while operating at 20-Gb/s data rate. The differential eye-opening of the proposed current-integrating logic (CIL) HR-PRBS generator is 1.6 V at 20-Gb/s date rate. � 2024 IEEE.