A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS

Abstract

The conventional power-hungry current and voltage-mode hybrid circuit topologies are not suitable for full-duplex(FD) front-end receivers, and they are not directly compatible with modern digital signal processing (DSP) cores as they suffer from low output differential eye-opening at high data rates. Moreover, they require extensive equalization and post-amplifier circuits to improve the eye-opening of the received signal at the cost of an additional power penalty and the increased circuit complexity. As a result, the overall energy-efficiency of the transceiver circuit becomes poor. To address this issue, in this work, the authors propose a half-rate StrongArm latch comparator based hybrid(HR-SALCH) for FD signaling over off-chip interconnect. The StrongArm latch comparator(SALC) circuit topology has the advantages of rail-to-rail voltage swing, digital equalization, and low static power dissipation and hence it is suitable candidate for realizing an energy-efficient receiver front-end hybrid circuit in FD off-chip communication. The proposed StrongArm latch comparator based hybrid(SALCH) is designed in 1.2 V, 65 nm CMOS at 6-Gb/s FD data rate over FR4-PCB interconnect of length 20 cm. The post-layout simulation results show that the proposed full-duplex transceiver deploying SALCH circuit topology has rail-to-rail output voltage swing with the timing jitter of 11 ps. The power consumption of the SALCH circuit topology is only 0.62 mW with an energy efficiency of 0.2 pJ/b at 6-Gb/s full-duplex operation. � 2024 IEEE.