A 2 7 -1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2�V, 65�nm CMOS

Abstract

In this work, we propose a 27-1, 20-Gb/s, low-power, charge-steering, half-rate pseudorandom bit sequence (PRBS) generator in 1.2 V, 65 nm CMOS. At the target data rate, the proposed charge-steering implementation has the lowest power consumption of 0.2 mW/Gb/s compared to the current-mode PRBS generator implementations, thanks to the discrete nature of the charge-steering latch circuit topology, which consumes a power of 22.3 ? W/Gb/s, whereas the CML latch consumes 60 ? W/Gb/s. The post-layout performance of the implementation shows a differential output voltage swing of 1.5 V, timing jitter of 5 ps and figure of merit of 0.038-pJ/bit at 20-Gb/s and it occupies an area of 0.026 mm 2. Thus, the proposed power efficient charge-steering half-rate PRBS generator implementation is an attractive candidate for on-chip bit-error-rate test and measurement applications. � 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.