FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation

Abstract

Integer arithmetic cores with multi-level logic realization can be suitably mapped over single or multiple slice columns on an FPGA with the scope to perform forward path pipelining wherever feasible. In this paper, we demonstrate the feasibility of a class of implementations where scan register functionality can be suitably appended across the registers of a finite state machine or pipelining registers. Absolute difference calculator, ternary accumulator and CORDIC architecture were chosen as representative examples for multi-level logic, whose careful FPGA realization guaranteed delay minimization, with the configured logic elements remaining underutilized. The scan register insertion exploited these sites by increasing the utility ratio of such logic elements, without incurring any hardware overhead or speed deterioration, compared to the original design without scan functionality. Our design philosophy has also outperformed the built-in IP cores that the FPGA CAD tool provides for certain functions, both in area and speed. � 2024 IEEE.