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Please use this identifier to cite or link to this item: http://idr.iitbbs.ac.in/jspui/handle/2008/2084
Title: Machine learning: Hit time finding with a neural network
Authors: Thalmeier R.
Yin H.
Aihara H.
Aziz T.
Bacher S.
Bahinipati S.
Barberio E.
Baroncelli Ti.
Baroncelli To.
Basith A.K.
Batignani G.
Bauer A.
Behera P.K.
Bertacchi V.
Bettarini S.
Bhuyan B.
Bilka T.
Bosi F.
Bosisio L.
Bozek A.
Buchsteiner F.
Caria G.
Casarosa G.
Ceccanti M.
Cervenkov D.
Czank T.
Dash N.
de Nuccio M.
Dole�al Z.
Forti F.
Friedl M.
Gobbo B.
Grimaldo J.A.M.
Hara K.
Higuchi T.
Irmler C.
Ishikawa A.
Jeon H.B.
Joo C.
Kaleta M.
Kandra J.
Kambara N.
Kang K.H.
Kody� P.
Kohriki T.
Koike S.
Komarov I.
Kumar M.
Kumar R.
Kun W.
Kvasnicka P.
la Licata C.
Lalwani K.
Lanceri L.
Lee J.Y.
Lee S.C.
Libby J.
Lueck T.
Mammini P.
Martini A.
Mayekar S.N.
Mohanty G.B.
Morii T.
Nakamura K.R.
Natkaniec Z.
Onuki Y.
Ostrowicz W.
Paladino A.
Paoloni E.
Park H.
Prasanth K.
Profeti A.
Rashevskaya I.
Rao K.K.
Rizzo G.
Resmi P.K.
Rozanska M.
Sahoo D.
Sasaki J.
Sato N.
Schultschik S.
Schwanda C.
Stypula J.
Suzuki J.
Tanaka S.
Tanigawa H.
Taylor G.N.
Tsuboyama T.
Urquijo P.
Vitale L.
Watanuki S.
Watanabe M.
Watson I.J.
Webb J.
Wiechczynski J.
Williams S.
Zani L.
Belle-II SVD Collaboration
Issue Date: 2018
Abstract: At the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, the double-sided silicon strip sub-detector of the Belle II experiment is read out by 1748 APV25 chips. FPGAs perform several calculations on the digitized signals. One of them will be "Hit Time Finding": the determination of the time and amplitude of the signal peaks of each event in real time using pre-programmed neural networks. This work analyses the possibility, precision and reliability of these calculations depending on various parameters. � Copyright owned by the author(s) under the terms of the Creative Commons.
URI: http://10.10.32.48:8080/jspui/handle/2008/2084
Appears in Collections:Research Publications

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