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Please use this identifier to cite or link to this item: http://idr.iitbbs.ac.in/jspui/handle/2008/1900
Title: Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids
Authors: Vasundhara, Mohanty B.K.
Panda G.
Puhan N.B.
Keywords: Acoustic feedback cancellation
Area-delay product
BLMS
Hearing aid
Low power
PFBLMS
Throughput rate
VLSI architecture
Issue Date: 2018
Abstract: Acoustic feedback is one of the major issues associated with the hearing aid users which limits the maximum amount of gain available for amplification and degrades the sound quality. In this paper, partitioned time-domain block LMS (PTBLMS) algorithm is proposed for efficient hardware realization of acoustic feedback cancellers (AFCs) in hearing aids. A full-parallel and a folded structure is derived using the proposed PTBLMS algorithm. The folded structure utilizing the time multiplexing of convolution and correlation operation and performing them in one arithmetic unit enables better hardware utilization. A low-complexity design is employed for realization of power normalization unit (for calculating normalized convergence factor) which involves squaring and division operations. The theoretical analysis illustrates that the proposed AFC structures offer L times higher throughput rate and requires proportionately less hardware resource than the existing one where L is the block length. ASIC synthesis results reveal that the proposed folded structure involves nearly 79% less area-delay product and 86% less energy per sample compared to the existing structure. � 2017, Springer Science+Business Media, LLC.
URI: http://dx.doi.org/10.1007/s00034-017-0619-1
http://10.10.32.48:8080/jspui/handle/2008/1900
Appears in Collections:Research Publications

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